Manufacture of semiconductor integrated circuits consists of a number of operations. A semiconductor wafer is first doped by diffusion with p-type or n-type material, then an insulating oxide layer is formed on the surface, after which conductive paths are formed by selective etching of the oxide layer. The semiconductor wafer is then doped with more impurities. The latter operations may be repeated a number of times. During some of these operations it is important that the surface of the wafer be essentially free of contaminants.
The contaminants to which this invention is directed are small particles. Particles on the surface of the wafer can interfere with some of the processing operations. For example, if a conductive path has been etched on the wafer surface and diffusion is to be accomplished through that path into the wafer, a particle located on that path and having a diameter of the order of the path width or greater will cause an unwanted gap in the diffusion pattern.
Unfortunately, these particles are generated during some of the processing steps. For example, when lines are etched in the oxide layer of a silicon wafer, some of the removed material can redeposit in particulate form elsewhere on the surface of the wafer. These particles must be removed from the surface of the wafer before the performance of subsequent operations with which they might interfere. The particles may be cleaned from the wafer by chemical removal (e.g. reaction with an acid or base), centrifugation, air-stream or water-jet cleaning, mechanical scrubbing, ultrasonic agitation or other known processes. The type of cleaning action depends on the contaminant form, the type of material to be cleaned, and the degree of cleanliness required.
With advances in integrated circuit manufacturing techniques, higher and higher circuit densities have been achieved, with correspondingly finer features on the semi-conductor surface. For example, the minimum feature size of a one-megabyte dynamic RAM chip will be about 1.25 microns, and production chips with architectural features of sub-micron size can be anticipated. Accordingly, even very small particles can cause problems and have to be removed from the wafer surface. Adhesion of such small particles to the surface of the wafer is believed to be due mainly to secondary valence interaction between the particle and the wafer surface (van der Waals forces). The ratio of the force of attraction to the weight of the particle increases as the size of the particle decreases.
Removal of sub-micron sized particles from a solid substrate is not a new problem. It has been a widely recognized problem for several decades. (See, "Cleaning of Electronic Device Components and Materials", Am. Soc. for Testing and Materials, 1958 and "Symposium on Cleaning and Material Related Processing for Electronics and Space Apparatus", Am. Soc. for Testing and Materials, 1962).
Difficulties of removal of particulate contamination with particles sizes below one micron are discussed. (See, J. M. Duffalo & J. R. Monkowski "Particulate Contamination and Device Performance", Solid State Technology, Mar. 1984, p. 109-114, and O. Hamberg and E. M. Shon "Particle Size Distribution on Surfaces in Clean Rooms", Proceedings-Institute of Environmental Sciences, 1984, p. 14-19). Hamberg and Shon in particular discuss the surface cleaning efficiency with such materials as trichlorotrifluoroethane marketed by E. I. DuPont de Nemours & Co., Inc. under the Freon Tf tradename. As the size of the particles to be removed decreases below one micron a very small proportion of the particles are removed by this method.
Indeed it is now generally believed that it is not possible to remove sub-micron sized particles from solid surfaces by known methods and this is an important issue to be resolved. (See, G. B. Larrabee "Chemical Technology of Microelectronics", Chemtech, Mar. 1985, p. 168-174).
It is therefore the object of the invention to provide an effective method and apparatus for removal of small particles from solid surfaces and in particular from the surfaces of semiconductor wafers.